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FAN9611 / FAN9612 -- Interleaved Dual BCM PFC Controllers
April 2011
FAN9611 / FAN9612 Interleaved Dual BCM PFC Controllers
Features
Sync-LockTM Interleaving Technology for 180 Out-of-Phase Synchronization Under All Conditions Automatic Phase Disable at Light Load Dead-Phase Detect Protection 2.0A Sink, 1.0A Source, High-Current Gate Drivers High Power Factor, Low Total Harmonic Distortion Voltage-Mode Control with (VIN)2 Feedforward Closed-Loop Soft-Start with User-Programmable Soft-Start Time for Reduced Overshoot Minimum Restart Frequency to Avoid Audible Noise Maximum Switching Frequency Clamp Brownout Protection with Soft Recovery Non-Latching OVP on FB Pin and Latching SecondLevel Protection on OVP Pin Open-Feedback Protection Power-Limit and Current Protection for Each Phase Low Startup Current of 80A Typical Works with DC and 50Hz to 400Hz AC Inputs
Description
The FAN9611/12 family of interleaved dual BoundaryConduction-Mode (BCM) Power-Factor-Correction (PFC) controllers operate two parallel-connected boost power trains 180 out of phase. Interleaving extends the maximum practical power level of the control technique from about 300W to greater than 800W. Unlike the continuous conduction mode (CCM) technique often used at higher power levels, BCM offers inherent zerocurrent switching of the boost diodes, which permits the use of less expensive diodes without sacrificing efficiency. Furthermore, the input and output filters can be smaller due to ripple current cancellation and effective doubling of the switching frequency. The converters operate with variable frequency, which is a function of the load and the instantaneous input / output voltages. The switching frequency is limited between 16.5kHz and 525kHz. The Pulse Width Modulators (PWM) implement voltage-mode control with input voltage feedforward. When configured for PFC applications, the slow voltage regulation loop results in constant on-time operation within a line cycle. This PWM method, combined with the BCM operation of the boost converters, provides automatic power factor correction. The controllers offers bias UVLO (10V / 7.5V for FAN9611 and 12.5V / 7.5V for FAN9612), input brownout, over-current, open-feedback, output overvoltage, and redundant latching over-voltage protections. Furthermore, the converters' output power is limited independently of the input RMS voltage. Synchronization between the power stages is maintained under all operating conditions.
Applications
100-1000W AC-DC Power Supplies Large Screen LCD-TV, PDP-TV, RP-TV Power High-Efficiency Desktop and Server Power Supplies Networking and Telecom Power Supplies Solar Micro Inverters
Figure 1. Simplified Application Diagram
(c) 2008 Fairchild Semiconductor Corporation FAN9611 / FAN9612 * Rev. 1.1.3 www.fairchildsemi.com
FAN9611 / FAN9612 -- Interleaved Dual BCM PFC Controllers
Ordering Information
Part Number
FAN9611MX FAN9612MX
Package
16-Lead, Small Outline Integrated Circuit (SOIC) 16-Lead, Small Outline Integrated Circuit (SOIC)
Packing Method
Tape and Reel Tape and Reel
Packing Quantity
2,500 2,500
This device passed wave soldering test by JESD22A-111.
Package Outlines
Figure 2. SOIC-16 (Top View)
Thermal Resistance Table
Thermal Resistance Package
16-Lead SOIC
Suffix
M
JL(1)
35C/W
JA(2)
50 - 120C/W(3)
Notes: 1. Typical JL is specified from semiconductor junction to lead. 2. Typical JA is dependent on the PCB design and operating conditions, such as air flow. The range of values covers a variety of operating conditions utilizing natural convection with no heatsink on the package. 3. This typical range is an estimate; actual values depend on the application.
(c) 2008 Fairchild Semiconductor Corporation FAN9611 / FAN9612 * Rev. 1.1.3
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FAN9611 / FAN9612 -- Interleaved Dual BCM PFC Controllers
Typical Application Diagram
VIN L2a D2 V LINE RZCD2 CIN RIN1 RZCD1 L1b AC IN EMI Filter RIN2 C5VB 1 2 3 4 RINHYST RMOT CSS RCOMP 7 CCOMP,LF CCOMP,HF 8 FB OVP 9 CVDD1 CINF CVDD2 COMP VIN 10 RCS1 RCS2 ROV2 5 6 AGND SS DRV2 12 PGND 11 ZCD1 ZCD2 5VB MOT CS1 16 CS2 15 VDD 14 DRV1 13 VBIAS Q1 RFB2 RFB1 L2b L1a D1 VOUT
COUT
RG1 RG2
Q2 ROV1
Figure 3. Typical Application Diagram
Block Diagram
Figure 4. Block Diagram
(c) 2008 Fairchild Semiconductor Corporation FAN9611 / FAN9612 * Rev. 1.1.3 www.fairchildsemi.com 3
FAN9611 / FAN9612 -- Interleaved Dual BCM PFC Controllers
Pin Configuration
Figure 5. Pin Layout (Top-View)
Pin Definitions
Pin #
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Name
ZCD1 ZCD2 5VB MOT AGND SS COMP FB OVP VIN PGND DRV2 DRV1 VDD CS2 CS1
Description
Zero Current Detector for Phase 1 of the interleaved boost power stage. Zero Current Detector for Phase 2 of the interleaved boost power stage. 5V Bias. Bypass pin for the internal supply, which powers all control circuitry on the IC. Maximum On-Time adjust for the individual power stages. Analog Ground. Reference potential for all setup signals. Soft-Start Capacitor. Connected to the non-inverting input of the error amplifier. Compensation Network connection to the output of the gM error amplifier Feedback pin to sense the converter's output voltage; inverting input of the error amplifier. Output Voltage monitor for the independent, second-level, latched OVP protection. Input Voltage monitor for brownout protection and input-voltage feedforward. Power Ground connection. Gate Drive Output for Phase 2 of the interleaved boost power stage. Gate Drive Output for Phase 1 of the interleaved boost power stage. External Bias Supply for the IC. Current Sense Input for Phase 2 of the interleaved boost power stage. Current Sense Input for Phase 1 of the interleaved boost power stage.
(c) 2008 Fairchild Semiconductor Corporation FAN9611 / FAN9612 * Rev. 1.1.3
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FAN9611 / FAN9612 -- Interleaved Dual BCM PFC Controllers
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.
Symbol
VDD VBIAS
Parameter
Supply Voltage to AGND & PGND 5VB Voltage to AGND & PGND Voltage On Input Pins to AGND (Except FB Pin) Voltage On FB Pin (Current Limited) Voltage On Output Pins to PGND (DRV1, DRV2)
Min.
-0.3 -0.3 -0.3 -0.3 -0.3
Max.
20.0 5.5 VBIAS + 0.3 VDD + 0.8 VDD + 0.3 2.5 0.05 +260
Unit
V V V V V A A C C C
IOH, IOL
Gate Drive Peak Output Current (Transient) Gate Drive Output Current (DC)
TL TJ TSTG
Lead Soldering Temperature (10 Seconds) Junction Temperature Storage Temperature -40 -65
+150 +150
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
VDD VINS ISNK ISRC Supply Voltage Range Signal Input Voltage
Parameter
Min.
9 0 1.5 0.8
Typ.
12
Max.
18 5
Unit
V V A A
Output Current Sinking (DRV1, DRV2) Output Current Sourcing (DRV1, DRV2)
(4)
2.0 1.0 5% 10% +125
LMISMATCH Boost Inductor Mismatch TA
Operating Ambient Temperature
-40
C
Note: 4. While the recommended maximum inductor mismatch is 10% for optimal current sharing and ripple-current cancellation, there is no absolute maximum limit. If the mismatch is greater than 10%, current sharing is proportionately worse, requiring over-design of the power supply. However, the accurate 180 out-of-phase synchronization is still maintained, providing current cancellation, although its effectiveness is reduced.
(c) 2008 Fairchild Semiconductor Corporation FAN9611 / FAN9612 * Rev. 1.1.3
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FAN9611 / FAN9612 -- Interleaved Dual BCM PFC Controllers
Electrical Characteristics
Unless otherwise noted, VDD = 12V, TJ = -40C to +125C. Currents are defined as positive into the device and negative out of the device.
Symbol
Supply ISTARTUP IDD IDD_DYM VON VOFF VHYS
Parameter
Startup Supply Current Operating Current Dynamic Operating Current
(5)
Conditions
VDD = VON - 0.2V Output Not Switching fSW = 50kHz; CLOAD = 2nF VDD Increasing VDD Decreasing VON - VOFF
Min.
Typ.
80 3.7 4
Max.
110 5.2 6 10.5 13.0 8.0
Unit
A mA mA V V V V V
UVLO Start Threshold, FAN9611 UVLO Start Threshold, FAN9612 UVLO Stop Threshold Voltage UVLO Hysteresis, FAN9611 UVLO Hysteresis, FAN9612
9.5 12.0 7.0
10.0 12.5 7.5 2.5 5.0 5.0
Bias Regulator (C5VB = 0.1F) TA = 25C; ILOAD = 1mA V5VB IOUT_MAX 5VB Output Voltage Maximum Output Current TA = 25C VEA Voltage Reference Total Variation Over Line, Load, and Temperature VFB = 1V to 3V; |VSS - VFB| 0.1V VSS = 3V; VFB = 2.9V VSS = 3V; VFB = 3.1V ISINK < 100A Total Variation Over Line, Load, and Temperature 4.8 5.0 2.95 2.91 -0.2 -13.7 4 4.5 0.0 50 TA = 25C VFB > VSS R = 125k R = 125k; VVIN = 2.5V; VCOMP > 4.5V; TA = 25C VFB > VPWM_OFFSET 1.16 3.4 1.25 5.0 120 -8 8 4.7 0.1 78 195 3.00 3.05 3.075 0.2 -4 12 V5VB 0.2 115 270 0 1.30 6.6 V V mA
5.2
Error Amplifier
IBIAS IOUT_SRC IOUT_SINK VOH VOL gM PWM
Input Bias Current Output Source Current Output Sink Current Output High Voltage Output Low Voltage Transconductance
A A A V V mho mV s V s
VRAMP,OFST PWM Ramp Offset tON,MIN VMOT tON,MAX Minimum On-Time Maximum On-Time Voltage Maximum On-Time
Maximum On-Time
Restart Timer (Each Channel) fSW,MIN fSW,MAX Minimum Switching Frequency Maximum Switching Frequency(5) 12.5 400 16.5 525 20.0 630 kHz kHz Frequency Clamp (Each Channel)
Continued on the following page...
(c) 2008 Fairchild Semiconductor Corporation FAN9611 / FAN9612 * Rev. 1.1.3
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FAN9611 / FAN9612 -- Interleaved Dual BCM PFC Controllers
Electrical Characteristics (Continued)
Unless otherwise noted, VDD = 12V, TJ = -40C to +125C. Currents are defined as positive into the device and negative out of the device.
Symbol
Current Sense VCS ICS tCS_DELAY VZCD_IN VZCD_H VZCD_L IZCD_SRC IZCD_SNK tZCD_DLY Output ISINK ISOURCE tRISE tFALL VO_UVLO IRVS ISS_MAX ISS_MIN VIN_BO IVINSNK
Parameter
CS Input Threshold Voltage Limit CS Input Current CS to Output Delay Input Voltage Threshold(4) Input High Clamp Voltage Input Low Clamp Voltage Source Current Capability Sink Current Capability(4) Turn-On Delay(5) OUTx Sink Current (5) OUTx Source Current Rise Time Fall Time Output Voltage During UVLO Reverse Current Withstand
(5) (5) (4)
Conditions
Min.
0.19
Typ.
0.21 85
Max.
0.23 0.2 100 0.1 1.2 -0.3 1 10
Unit
V A ns V V V mA mA ns A A
VCSX = 0V to 1V CS Stepped from 0V to 5V
-0.2
Zero Current Detection -0.1 IZCD = 0.5mA IZCD = -0.5mA 0.8 -0.7 0 1.0 -0.5
ZCDx to OUTx VOUTx = VDD/2; CLOAD = 0.1F VOUTx = VDD/2; CLOAD = 0.1F CLOAD = 1nF, 10% to 90% CLOAD = 1nF, 90% to 10% VDD = 5V; IOUT = 100A
180 2.0 1.0 10 5 500 25 20 1
ns ns V mA
Soft-Start (CSS = 0.1F) Maximum Soft-Start Current Minimum Soft-Start Current Input Brownout Threshold VIN Sink Current VVIN > 1.1V VVIN < 0.8V
(5)
VCOMP < 3.0V VCOMP > 4.5V
-7 -0.40 0.76 -0.2 1.4 3.1 3.6
-5 -0.25 0.925 2 3.7 4.0
-3 -0.10 1.10 0.2 2.5 4.3 4.3
A A V A A V
Input Brown-Out Protection
Input-Voltage Feedforward Range VFF_UL VFF_RATIO VIN Feedforward Upper Limit (5) VFF_UL / VIN_BO
(5)
Phase Management VPH,DROP VPH,ADD Phase Dropping Threshold Phase Adding Threshold VCOMP Decreasing, Transition from 2 to 1 Phase, TA = 25C VCOMP Increasing, Transition from 1 to 2 Phase, TA = 25C TA = 25C DRV1=DRV2=0V FB Decreasing DRV1=DRV2=0V 3.36 0.66 0.86 0.73 0.93 0.80 1.00 V V
Over-Voltage Protection Using FB Pin - Cycle-by-Cycle (Input) VOVPNL Non-Latching OVP Threshold (+8% above VOUT_NOMINAL) 3.15 3.25 0.24 3.50 3.65 3.35 V V V
VOVPNL_HYS OVP Hysteresis VOVPLCH Latching OVP Threshold (+15%)
Over-Voltage Protection Using OVP Pin - Latching (Input) Note: 5. Not tested in production.
(c) 2008 Fairchild Semiconductor Corporation FAN9611 / FAN9612 * Rev. 1.1.3 www.fairchildsemi.com 7
FAN9611 / FAN9612 -- Interleaved Dual BCM PFC Controllers
Theory of Operation
1. Boundary Conduction Mode
The boost converter is the most popular topology for power factor correction in AC-to-DC power supplies. This popularity can be attributed to the continuous input current waveform provided by the boost inductor and to the fact that the boost converter's input voltage range includes 0V. These fundamental properties make close to unity power factor easier to achieve. There are many fundamental differences in CCM and BCM operations and the respective designs of the boost converter. The FAN9611/12 utilizes the boundary conduction mode control algorithm. The fundamental concept of this operating mode is that the inductor current starts from zero in each switching period, as shown in the lower waveform in Figure 7. When the power transistor of the boost converter is turned on for a fixed amount of time, the peak inductor current is proportional to the input voltage. Since the current waveform is triangular, the average value in each switching period is also proportional to the input voltage. In the case of a sinusoidal input voltage waveform, the input current of the converter follows the input voltage waveform with very high accuracy and draws a sinusoidal input current from the source. This behavior makes the boost converter in BCM operation an ideal candidate for power factor correction. This mode of control of the boost converter results in a variable switching frequency. The frequency depends primarily on the selected output voltage, the instantaneous value of the input voltage, the boost inductor value, and the output power delivered to the load. The operating frequency changes as the input voltage follows the sinusoidal input voltage waveform. The lowest frequency operation corresponds to the peak of the sine waveform at the input of the boost converter. Even larger frequency variation can be observed as the output power of the converter changes, with maximum output power resulting in the lowest operating frequency. Theoretically, under zero-load condition, the operating frequency of the boost converter would approach infinity. In practice, there are natural limits to the highest switching frequency. One such limiting factor is the resonance between the boost inductor and the parasitic capacitances of the MOSFET, the diode, and the winding of the choke, in every switching cycle. Another important characteristic of the BCM boost converter is the high ripple current of the boost inductor, which goes from zero to a controlled peak value in every switching period. Accordingly, the power switch is stressed with high peak current. In addition, the high ripple current must be filtered by an EMI filter to meet high-frequency noise regulations enforced for equipment connecting to the mains. The effects usually limit the practical output power level of the converter.
Figure 6. Basic PFC Boost Converter The boost converter can operate in continuous conduction mode (CCM) or in boundary conduction mode (BCM). These two descriptive names refer to the current flowing in the energy storage inductor of the boost power stage.
Figure 7. CCM vs. BCM Control As the names indicate, the current in Continuous Conduction Mode (CCM) is continuous in the inductor; while in Boundary Conduction Mode (BCM), the new switching period is initiated when the inductor current returns to zero.
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FAN9611 / FAN9612 -- Interleaved Dual BCM PFC Controllers
2. Interleaving
The FAN9611/12 control IC is configured to control two boost converters connected in parallel, both operated in boundary conduction mode. In this arrangement, the input and output voltages of the two parallel converters are the same and each converter is designed to process approximately half the total output power.
a sine square function. Eliminating the line frequency component from the feedback system is imperative to maintain low total harmonic distortion (THD) in the input current waveform. The pulse width modulator implements voltage mode control. This control method compares an artificial ramp to the output of the error amplifier to determine the desired on-time of the converter's power transistor to achieve output voltage regulation.
Figure 9. PWM Operation Figure 8. Interleaved PFC Boost Operation Parallel power processing is penalized by the increased number of power components, but offers significant benefits to keep current and thermal stresses under control and to increase the power handling capability of the otherwise limited BCM PFC control solution. Furthermore, the switches of the two boost converters can be operated 180 degrees out of phase from each other. The control of parallel converters operating 180 degrees out of phase is called interleaving. Interleaving provides considerable ripple current reduction at the input and output terminals of the power supply, which favorably affects the input EMI filter requirements and reduces the high-frequency RMS current of the power supply output capacitor. There is an obvious difficulty in interleaving two BCM boost converters. Since the converter's operating frequency is influenced by component tolerances in the power stage and in the controller, the two converters operate at different frequencies. Therefore special attention must be paid to ensure that the two converters are locked to 180-degree out-of-phase operation. Consequently, synchronization is a critical function of an interleaved boundary conduction mode PFC controller. It is implemented in the FAN9611/12 using proprietary and dedicated circuitry called Sync-LockTM interleaving technology. In FAN9611/12, there are two PWM sections corresponding to the two parallel power stages. For proper interleaved operation, two independent 180degree out-of-phase ramps are needed; which necessitates the two pulse width modulators. To ensure that the two converters process the same amount of power, the artificial ramps have the same slope and use the same control signal generated by the error amplifier.
4. Input-Voltage Feedforward
Basic voltage-mode control, as described in the previous section, provides satisfactory regulation performance in most cases. One important characteristic of the technique is that input voltage variation to the converter requires a corrective action from the error amplifier to maintain the output at the desired voltage. When the error amplifier has adequate bandwidth, as in most DC-DC applications, it is able to maintain regulation within a tolerable output voltage range during input voltage changes. On the other hand, when voltage-mode control is used in power factor corrector applications; the error amplifier bandwidth, and its capability to quickly react to input voltage changes, is severely limited. In these cases, the input voltage variation can cause excessive overshoot or droop at the converter output as the input voltage goes up or down. To overcome this shortcoming of the voltage-mode PWM circuit in PFC applications, input-voltage feedforward is often employed. It can be shown mathematically that a PWM ramp proportional to the square of the input voltage rejects the effect of input voltage variations on the output voltage and eliminates the need of any correction by the error amplifier.
3. Voltage Regulation, Voltage Mode Control
The power supply's output voltage is regulated by a negative feedback loop and a pulse width modulator. The negative feedback is provided by an error amplifier that compares the feedback signal at the inverting input to a reference voltage connected to the non-inverting input of the amplifier. Similar to other PFC applications, the error amplifier is compensated with high DC gain for accurate voltage regulation, but very low bandwidth to suppress line frequency ripple present across the output capacitor of the converter. The line frequency ripple is the result of the constant output power of the converter and the fact that the input power is the product of a sinusoidal current and a sinusoidal voltage thus follows
(c) 2008 Fairchild Semiconductor Corporation FAN9611 / FAN9612 * Rev. 1.1.3
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FAN9611 / FAN9612 -- Interleaved Dual BCM PFC Controllers
At startup condition and in the unlikely case of missing zero current detection, the lack of an oscillator would mean that the converter stops operating. To overcome these situations, a restart timer is employed to kick start the controller and provide the first turn-on command, as shown in Figure 12.
Figure 10. Input-Voltage Feedforward When the PWM ramp is made proportional to the input voltage squared, the system offers other noteworthy benefits. The first is the input voltage-independent small signal gain of the closed loop power supply, which makes compensation of the voltage regulation loop much easier. The second side benefit is that the output of the error amplifier becomes directly proportional to the input power of the converter. This phenomenon is very significant and it is re-visited in Section 9 describing light-load operation.
Figure 12. PWM Cycle Start
6. Terminating the Conduction Interval
Terminating the conduction period of the boost transistor in boundary conduction mode controllers is similar to any other pulse width modulator. During normal operation, the PWM comparator turns off the power transistor when the ramp waveform exceeds the control voltage provided by the error amplifier. In the FAN9611/12 and in similar voltage-mode PWMs, the ramp is a linearly rising waveform at one input of the comparator circuit.
Maximum On-Time S Current Limit Q DRV
5. Starting a PWM Cycle
The principle of boundary conduction mode calls for a pulse width modulator able to operate with variable frequency and initiate a switching period whenever the current in the boost inductor reaches zero. Therefore, BCM controllers cannot utilize a fixed frequency oscillator circuit to control the operating frequency. Instead, a zero current detector is used to sense the inductor current and turn on the power switch once the current in the boost inductor reaches zero. This process is facilitated by an auxiliary winding on the boost inductor. The voltage waveform of the auxiliary winding can be used for indirect detection of the zero inductor current condition of the boost inductor. Therefore it should be connected to the zero current detect input, as shown in Figure 11.
RD Q
PWM
Figure 13. Conduction Interval Termination In addition to the PWM comparator, the current limit circuit and a timer circuit limiting the maximum on-time of the boost transistor can also terminate the gate drive pulse of the controller. These functions provide protection for the power switch against excessive current stress.
7. Protecting the Power Components
In general, power converters are designed with adequate margin for reliable operation under all operating conditions. However, it might be difficult to predict dangerous conditions under transient or certain fault situations. Therefore, the FAN9611/12 contains dedicated protection circuits to monitor the individual peak currents in the boost inductors and in the power transistors. Furthermore, the boost output voltage is sensed by two independent mechanisms to provide over-voltage protection for the power transistors, rectifier diodes, and the output energy storage capacitor of the converter.
Figure 11. Simple Zero-Current Detection Method The auxiliary winding can also be used to generate bias for the PFC controller when an independent bias power supply is not present in the system.
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FAN9611 / FAN9612 -- Interleaved Dual BCM PFC Controllers
8. Power Limit
The architecture and operating principle of FAN9611/12 also provides inherent input power limiting capability.
Figure 15. Automatic Phase-Control Operation
10. Brownout Protection with Soft Recovery
Figure 14. On-Time vs. VIN_RMS When the slope of the PWM ramp is made proportional to the square of the input RMS voltage, the maximum on-time of the boost power switch becomes inversely proportional to the square of VIN,RMS, as represented in Figure 14. In boundary-conduction mode, the peak current of the boost transistor is proportional to its on time. Therefore, controlling the maximum pulse width of the gate drive signal according to the curve shown is an effective method to implement an input-voltage independent power limit for the boost PFC. An additional protection function usually offered by PFC ICs is input brownout protection to prevent the converter from operating below a user-defined minimum input voltage level. For this function to work, the input voltage of the converter is monitored. When the voltage falls below the brownout protection threshold, the converter stops working. The output voltage of the boost converter falls until the load stops drawing current from the output capacitor or until the input voltage gets back to its nominal range and operation resumes. As the output falls, the voltage at the feedback pin falls proportionally, according to the feedback divider ratio. To facilitate soft recovery after a brownout condition, the soft-start capacitor - which is also the reference voltage of the error amplifier - is pulled lower by the feedback network. This effectively pre-conditions the error amplifier to provide closed-loop, soft-start-like behavior during the converter's recovery from a brownout situation. Once the input voltage goes above the brownout protection threshold, the converter resumes normal operation. The output voltage rises back to the nominal regulation level following the slowly rising voltage across the soft-start capacitor.
9. Light-Load Operation (Phase Management)
One of the parameters determining the operating frequency of a boundary conduction mode converter is the output power. As the load decreases, lower peak currents are commanded by the pulse width modulator to maintain the output voltage at the desired set point. Lower peak current means shorter on-time for the power transistor and shorter time interval to ramp the inductor current back to zero at any given input voltage. As a result, the operating frequency of the converter increases under light load condition. As the operating frequency and corresponding switching losses increase, conduction losses diminish at the same time. Therefore, the power losses of the converter are dominated by switching losses at light load. This phenomenon is especially evident in a BCM converter. To improve light-load efficiency, FAN9611/12 disables one of the two interleaved boost converters automatically when the output power falls below approximately 13% of the maximum power limit level. By managing the number of phases used at light load, the FAN9611/12 can maintain high efficiency for a wider load range of the power supply. Normal interleaved operation of the two boost converters resumes automatically once the output power exceeds approximately 18% of the maximum power limit level of the converter. By adjusting maximum on-time (using RMOT), the phase management thresholds can be adjusted upward, described in the "Adjusting the Phase-Management Thresholds" section of this datasheet.
11. Soft Starting the Converter
During startup, the boost converter peak charges its output capacitor to the peak value of the input voltage waveform. The final voltage level, where the output is regulated during normal operation, is reached after the converter starts switching. There are two fundamentally different approaches used in PWM controllers to control the startup characteristics of a switched-mode power supply. Both methods use some kind of soft-start mechanism to reduce the potential overshoot of the converter's output after the desired output voltage level is reached. The first method is called open-loop soft-start and relies on gradually increasing the current or power limit of the converter during startup. In this case, the voltage error amplifier is typically saturated, commanding maximum current until the output voltage reaches its final value. At that time, the voltage between the error amplifier inputs changes polarity and the amplifier slowly comes out of saturation. While the error amplifier recovers and before it starts controlling the output voltage, the converter operates with full power. Thus, output voltage overshoot is unavoidable in converters utilizing the open-loop softstart scheme.
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FAN9611 / FAN9612 -- Interleaved Dual BCM PFC Controllers
This method is especially dangerous in power-factorcorrector applications because the error amplifier's bandwidth is typically limited to a very low crossover frequency. The slow response of the amplifier can cause considerable overshoot at the output.
FAN9611/12 employs closed-loop soft-start where the reference voltage of the error amplifier is slowly increased to its final value. When the current and power limits of the converter are properly taken into consideration, the output voltage of the converter follows the reference voltage. This ensures that the error amplifier stays in regulation during soft start and the output voltage overshoot can be eliminated.
Functional Description
1. Detecting Zero Inductor Current (ZCD1, ZCD2)
Each ZCD pin is internally clamped close to 0V (GND). Any capacitance on the pin is ineffective in providing any delay in ZCD triggering. The internal sense circuit is a true differentiator to catch the valley of the drain waveforms. The resistor between the auxiliary winding of the boost inductor and the ZCD pin is only used for current limiting. The maximum source current during zero current detection must be limited to 0.5mA. Source and sink capability of the pin is about 1mA, providing sufficient margin for the higher source current required during the on-time of the power MOSFETs. Figure 17. 5V Bias
3. Maximum On-Time Control (MOT)
Maximum on-time, MOT, (of the boost MOSFET) is set by a resistor to analog ground (AGND). The FAN9611/12 implements input-voltage feedforward. The maximum on-time is a function of the RMS input voltage. The voltage on the MOT pin is 1.25V during operation (constant DC voltage). The maximum on-time of the power MOSFETs can be approximated by:
tON , MAX RMOT 120 1012
Figure 16. Zero-Current Detect Circuit The RZCD resistor value can be approximated by:
R ZCD V N AUX 1 O 0.5 mA 2 N BOOST
2.4 1 2 1.25 VINSNS , PK
(2)
(1)
where VINSNS,PK is the peak of the AC input voltage as measured at the VIN pin (must be divided down, see the VIN pin description).
2. 5V Bias Rail (5VB)
This is the bypass capacitor pin for the internal 5V bias rail powering the control circuitry. The recommended capacitor value is 220nF. At least a 100nF, good-quality, high-frequency, ceramic capacitor should be placed in close proximity to the pin. The 5V rail is a switched rail. It is actively held LOW when the FAN9611/12 is in under-voltage lockout. Once the UVLO turn-on threshold is exceeded at the VDD pin, the 5V rail is turned on, providing a sharp edge that can be used as an indication that the chip is running. Potentially, this behavior can be utilized to control the inrush current limiting circuit.
(c) 2008 Fairchild Semiconductor Corporation FAN9611 / FAN9612 * Rev. 1.1.3 12
Figure 18. Maximum On-Time Control (MOT)
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FAN9611 / FAN9612 -- Interleaved Dual BCM PFC Controllers
4. Analog Ground (AGND) and Power Ground (PGND)
Analog ground connection (AGND) is the GND for all control logic biased from the 5V rail. Internally, the AGND and PGND pins are tied together by two antiparallel diodes to limit ground bounce difference due to bond wire inductances during the switching actions of the high-current gate drive circuits. It is recommended to connect AGND and PGND pins together with a short, low-impedance trace on the PCB (right under the IC). PGND is the reference potential (0V) for the highcurrent gate-drive circuit. Two bypass capacitors should be connected between the VDD pin and the PGND pin. One is the VDD energy storage capacitor, which provides bias power during startup until the bootstrap power supply comes up. The other capacitor shall be a goodquality ceramic bypass capacitor, as close as possible to PGND and VDD pins to filter the high peak currents of the gate driver circuits. The value of the ceramic bypass capacitor is a strong function of the gate charge requirement of the power MOSFETs and its recommended value is between 1F and 4.7F to ensure proper operation.
voltage stays flat or even decays while the SS voltage keeps rising. This is a problem if closed-loop soft-start should be maintained. By clamping the SS voltage to the FB pin, this problem can be mitigated. Furthermore, during brownout condition, the output voltage of the converter might fall, which is reflected at the FB pin. When FB voltage goes 0.5V below the voltage on the SS pin, it starts discharging the soft-start capacitor. The soft-start capacitor remains 0.5V above the FB voltage. When the brownout condition is over, the converter returns to normal operation gracefully, following the slow ramp up of the soft-start capacitor at the non-inverting input of the error amplifier.
5. Soft-Start (SS)
Soft-start is programmed with a capacitor between the SS pin and AGND. This is the non-inverting input of the transconductance (gM) error amplifier. At startup, the soft-start capacitor is quickly pre-charged to a voltage approximately 0.5V below the voltage on the feedback pin (FB) to minimize startup delay. Then a 5A current source takes over and charges the soft-start capacitor slowly, ramping up the voltage reference of the error amplifier. By ramping up the reference slowly, the voltage regulation loop can stay closed, actively controlling the output voltage during startup. While the SS capacitor is charging, the output of the error amplifier is monitored. In case the error voltage (COMP) ever exceeds 3.5V, indicating that the voltage loop is close to saturation, the 5A soft-start current is reduced. Therefore, the soft start is automatically extended to reduce the current needed to charge the output capacitor, reducing the output power during startup. This mechanism is integrated to prevent the voltage loop from saturation. The charge current of the soft-start capacitor can be reduced from the initial 5A to as low as 0.5A minimum. In addition to modulating the soft-start current into the SS capacitor, the SS pin is clamped 0.2V above the FB pin. This is useful in preventing the SS capacitor from running away from the FB pin and defeating the closedloop soft-start. During the zero crossing of the input source waveform, the input power is almost zero and the output voltage can not be raised. Therefore the FB Figure 19. Soft-Start Programming
6. Error Amplifier Compensation (COMP)
COMP pin is the output of the error amplifier. The voltage loop is compensated by a combination of RS and CS to AGND at this pin. The control range of the error amplifier is between 0.195V and 4.3V. When the COMP voltage is below about 0.195V, the PWM circuit skips pulses. Above 4.3V, the maximum on-time limit terminates the conduction of the boost switches. Due to the input-voltage feedforward, the output of the error amplifier is proportional to the input power of the converter, independent of the input voltage. In addition, also due to the input-voltage feedforward, the maximum power capability of the converter and the loop gain is independent of the input voltage. The controller's phasemanagement circuit monitors the error amplifier output and switches to single-phase operation when the COMP voltage falls below 0.73V and returns to two-phase operation when the error voltage exceeds 0.93V. These thresholds correspond to about 13% and 18% of the maximum power capability of the design.
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FAN9611 / FAN9612 -- Interleaved Dual BCM PFC Controllers
Figure 20. Error Amplifier Compensation Circuitry
7. Output Voltage Feedback (FB)
The feedback pin receives the divided-down output voltage of the converter. In regulation, the FB pin should be 3V, which is the reference used at the non-inverting input of the error amplifier. Due to the gM type error amplifier, the FB pin is always proportional to the output voltage and can be used for over-voltage protection as well. A non-latching over-voltage detection circuit monitors the FB pin and prevents the boost MOSFETs from turning on when the FB voltage exceeds 3.25V. Operation resumes automatically when the FB voltage returns to its nominal 3V level. The open feedback detection circuit is also connected to the FB pin. Since the output of the boost converter is charged to the peak of the input AC voltage when power is applied to the power supply, the detection circuit monitors the presence of this voltage. If the FB pin is below 0.5V, which would indicate a missing feedback divider (or wrong value causing dangerously-high regulation voltage), the FAN9611/12 does not send out gate drive signals to the boost transistors.
External Components Internal Circuits To SS
VOUT
8. Secondary Output Voltage Sense (OVP)
A second-level latching over-voltage protection can be implemented using the OVP pin of the controller. The threshold of this circuit is set to 3.5V. There are two ways to program the secondary OVP. Option 1, as shown in Figure 22, is to connect the OVP pin to the FB pin. In addition to the standard nonlatching OVP (set at ~8%), this configuration provides a second OVP protection (set at ~15%), which is latched. In the case where redundant over-voltage protection is preferred (also called double-OVP protection), a second separate divider from the output voltage can be used, as shown by Option 2 in Figure 22. In this case, the latching OVP protection level can be independently established below or above the non-latching OVP threshold, which is based on the feedback voltage (at the FB pin). If latching OVP protection is not desired at all, the OVP pin should be grounded (Option 3).
To Phase / Gain Control
+200 mV, -500 mV, Clamp
gM Error Amplifier
8 FB
Figure 22. Secondary Over-Voltage Protection Circuit Figure 21. Output-Voltage Feedback Circuit
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FAN9611 / FAN9612 -- Interleaved Dual BCM PFC Controllers
9. Input Voltage Sensing (VIN)
The input AC voltage is sensed at the VIN pin. The input voltage is used in three functions: input under-voltage lockout (brownout protection), input over-voltage protection, and input voltage feedforward in the PWM control circuit. All the functions require the RMS value of the input voltage waveform. Since the RMS value of the AC input voltage is directly proportional to its peak, it is sufficient to find the peak instead of the more complicated and slower method of integrating the input voltage over a half line cycle. The internal circuit of the VIN pin works with peak detection of the input AC waveforms. One of the important benefits of this approach is that the peak indicates the correct RMS value even at no load when the HF filter capacitor at the input side of the boost converter is not discharged around the zero crossing of the line waveform. Another notable benefit is that during line transients, when the peak exceeds the previously measured value, the inputvoltage feedforward circuit can react immediately, without waiting for a valid integral value at the end of the half line period. Furthermore, lack of zero crossing
detection could fool the integrator while the peak detector works properly during light-load operation. The valid range for the peak of the AC input is between approximately 0.925V and 3.7V. This range is optimized for universal input voltage range of operation. If the peak of the sense voltage remains below the 0.925V threshold, input under-voltage or brownout condition is declared and the FAN9611/12 stops operating. When the VIN voltage exceeds 3.7V, the FAN9611/12 input voltage sense circuit saturates and the feedforward circuit is not able to follow the input any higher. Consequently, the slope of the PWM ramp remains constant corresponding to the VIN = 3.7V level amplitude for any VIN voltage above 3.7V. The input voltage is measured by a tracking analog-todigital converter, which keeps the highest value (peak voltage) of the input voltage waveform. Once a measurement is taken, the converter tracks the input for at least 12ms before a new value is taken. This delay ensures at least one new peak value is captured before the new value is used.
Figure 23. Input Voltage Sensing Circuit
The measured peak value is then used in the following half-line cycle while a new measurement is executed to be used in the next half line cycle. This operation is synchronized to the zero crossing of the line waveform. Since the input voltage measurement is held steady during the line half periods, this technique does not feed any AC ripple into the control loop. If line zero crossing detection is missing, the FAN9611/12 measures the input voltage in every 32ms; it can operate from a DC
input as well. The following figures provide detail about the input voltage sensing method of the controller. As shown in the waveforms, input voltage feedforward is instantaneous when the line voltage increases and has a half line cycle delay when the input voltage decreases. Any increase in input voltage would cause output over voltage due to the slow nature of the voltage regulation loop. This is successfully mitigated by the immediate action of the input-voltage feedforward circuit.
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FAN9611 / FAN9612 -- Interleaved Dual BCM PFC Controllers
Figure 24. Input Voltage Sensing Waveforms
10. Gate Drive Outputs (DRV1; DRV2)
High-current driver outputs DRV1 and DRV2 have the capability to sink a minimum of 2A and source 1A. Due to the low impedance of these drivers, the 1A source current must be actively limited by an external gate resistor. The minimum external gate resistance is:
VDD (3) 1A To take advantage of the higher sink current capability of the drivers, the gate resistor can be bypassed by a small diode to facilitate faster turn-off of the power MOSFETs. Traditional fast turn-off circuit using a PNP transistor instead of a simple bypass diode can be considered as well. RGATE
The purpose of the MillerDriveTM architecture is to speed switching by providing high current during the Miller plateau region when the gate-drain capacitance of the MOSFET is being charged or discharged as part of the turn-on / turn-off process. The output pin slew rate is determined by VDD voltage and the load on the output. It is not user adjustable, but if a slower rise or fall time at the MOSFET gate is needed, a series resistor can be added.
VDD
It is also imperative that the inductance of the gate drive loop is minimized to avoid excessive ringing. If optimum layout is not possible or the controller is placed on a daughter card, it is recommended to use an external driver circuit located near the gate and source terminals of the boost MOSFET transistors. Small gate charge power MOSFETs can be driven by a single 1A gate driver, such as the FAN3111C; while higher gate charge devices might require higher gate drive current capable devices, such as the single-2A FAN3100C or the dual2A FAN3227C family of drivers.
VOUT
11. MillerDriveTM Gate Drive Technology
FAN9611/12 output stage incorporates the MillerDriveTM architecture shown in Figure 25. It is a combination of bipolar and MOS devices which are capable of providing large currents over a wide range of supply voltage and temperature variations. The bipolar devices carry the bulk of the current as OUT swings between 1/3 to 2/3 VDD and the MOS devices pull the output to the high or low rail.
(c) 2008 Fairchild Semiconductor Corporation FAN9611 / FAN9612 * Rev. 1.1.3
Figure 25. Current-Sense Protection Circuits
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FAN9611 / FAN9612 -- Interleaved Dual BCM PFC Controllers
12. Bias Supply (VDD)
This is the main bias source for the FAN9611/12. The operating voltage range is between 8V and 18V. The VDD voltage is monitored by the under-voltage lockout (UVLO) circuit. At power-up, the VDD voltage must exceed 10.0V (0.5V) for FAN9611 and exceed 12.5V (0.5V) for FAN9612 to enable operation. Both the FAN9611 and the FAN9612 stops operating when the VDD voltage falls below 7.5V (0.5V). See PGND pin description for important bypass information.
13. Current-Sense Protection (CS1, CS2)
The FAN9611/12 uses independent over-current protection for each of the power MOSFETs. The current-sense thresholds at the CS1 and CS2 pins are approximately 0.2V. The current measurements are strictly for protection purposes and are not part of the control algorithm. The pins can be directly connected to the non-grounded end of the current-sense resistors because the usual R-C filters of the leading-edge current spike are integrated in the IC. Figure 26. Current-Sense Protection Circuits The time constant of the internal filter is approximately:
27k 5pF 130ns
or
P
1 1.2MHz 2 27k 5 pF
(4)
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FAN9611 / FAN9612 -- Interleaved Dual BCM PFC Controllers
Application Information
1. Synchronization and Timing Functions
The FAN9611/12 employs a sophisticated synchronization sub-system. At the heart of the system is a dual-channel switching-frequency detector that measures the switching period of each channel in every switching cycle and locks their operating phase 180 degrees out of phase from each other. The slower operating frequency channel is dominant, but there is no master-slave arrangement. Moreover, as the frequency constantly changes due to the varying input voltage, either channel can be the slower dominant channel. As opposed to the most common technique, where the phase relationship between the channels is provided by changing the on-time of one of the MOSFETs, the FAN9611/12 controls the phase relationship by inserting a turn-on delay before the next switching period starts for the faster running phase. As shown in the [1] literature , the on-time modulation technique is not stable under all operating conditions, while the off-time modulation (or delaying the turn-on) is unconditionally stable under all operating conditions. a. Restart Timer and Dead-Phase Detect Protection
2. FAN9612 Startup with 12V Bias (Less than UVLO)
The FAN9612 (not FAN9611) is designed so that the controller can start even if the auxiliary bias voltage is less than the controller's under-voltage lockout start threshold. This is useful if the auxiliary power is 12V or below. This configuration also allows bias power designs using a bootstrap winding to start the FAN9612 without a dedicated startup resistor. In the boost PFC topology, the output voltage is precharged to the peak line voltage by the boost diode. As soon as voltage is present at the output of the boost converter, current starts to flow through the feedback resistors from the boost output to GND. Using an external low-voltage MOSFET in series with the lower resistor in the feedback divider, as shown in Figure 27; this current can be diverted to charge the VDD bypass capacitor of the controller. The upper resistor becomes a current source to charge the capacitor. To accomplish this, a small external diode should be connected between the VDD and FB pins. As VDD rises past the under-voltage lockout threshold of the IC, the 5V reference is turned on, which turns on the external MOSFET and connects the resistor of the feedback divider to ground. The IC checks if the FB voltage is below 3.22V, ensuring that the FB pin is in its normal operating voltage range, before enabling the rest of the IC operation. The diode between the FB pin and the VDD pin is reverse biased and the FB pin reverts to its normal role of output voltage sensing. A simplified circuit implementation for this proprietary startup method is shown in Figure 27. If, for whatever reason, the bias to the IC drops below the under-voltage lockout level, the startup process is repeated.
The restart timer is an integral part of the Sync-LockTM synchronizing circuit. It ensures exact 180-degree outof-phase operation in restart timer operation. This is an important safety feature. In the case of a non-operating phase due to no ZCD detection, missing gate drive connection (for example no gate resistor), one of the power components failing in an open circuit, or similar errors, the other phase is locked into restart timer operation, preventing it from trying to deliver full power to the load. This is called the dead-phase detect protection. The restart timer is set to approximately 16.5kHz, just above the audible frequency range, to avoid any acoustic noise generation. b. Frequency Clamp
Just as the restart timer, the frequency clamp is integrated into the synchronization and ensures exact 180-degree out-of-phase operation when the operating frequency is limited. This might occur at very light-load operation or near the zero crossing region of the line voltage waveform. Limiting the switching frequency at light load can improve efficiency, but has a negative effect on power factor since the converter also enters true DCM operation. The frequency clamp is set to approximately 525kHz.
Figure 27. Simplified FAN9612 Startup Circuit Using the Output Feedback Resistors to Provide a Charging Current
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FAN9611 / FAN9612 -- Interleaved Dual BCM PFC Controllers
3. Adjusting the Output Voltage with Load
In some applications, the output voltage of the PFC boost converter is decreased at low power levels to boost the light load efficiency of the power supply. Implementing this function with a circuit external to the FAN9611/12 is straightforward because the error amplifier reference (the positive input) is available on the soft-start (SS) pin, as shown in Figure 28. In the FAN9611/12 architecture, the power of the converter is proportional to the voltage on the COMP pin, minus a small offset. The voltage on the COMP pin is monitored to determine the operating power of the supply. Therefore the voltage on the SS pin can be adjusted lower to achieve the desired lower output voltage. Several possible implementations to adjust the output voltage of the boost stage at light load are described in the application note AN-8021. It includes the universal output voltage adjust implementation which is modulated by input voltage to avoid the boost converter becoming a peak rectifier at high line and light load.
The default thresholds can be adjusted upward based on the application requirement; for example, to meet the Energy STAR 5.0 or the Climate Savers Computing efficiency requirements at 20% of the load. The phase drop threshold can be adjusted upward (for example to 25%) by adjusting the maximum on time.
Figure 29. Adjusting Phase Management Thresholds Since the phase management threshold is fixed at 13% and 18% of the maximum power limit level, the actual power management threshold as a percentage of nominal output power can be adjusted by the ratio between nominal power and maximum power limit level as shown in Figure 29. The second plot shows an example where the maximum power limit level is 1.4 times of nominal output power. By adjusting the maximum on-time (using RMOT), the phase management thresholds can be adjusted upward. Phase management is implemented such that the output of the error amplifier (VCOMP) does not have to change when the system toggles between single-phase and two-phase operations, as shown in Figure 30. The output of the error amplifier is proportional to the output power of the converter independently, whether one or both phases are operating in the power supply. Furthermore, because the maximum on-time limit is applied independently to each pulse-width modulator, the power handling capability of the converter with only one phase running is approximately half of the total output power that can be delivered when both phases are utilized. Additional details on adjusting phase management are provided in the application note AN-6086.
Figure 28. FAN9611/12 Error Amplifier Configuration
4. Adjusting the Output Voltage with Input Voltage
In some applications, the output voltage of the PFC boost converter is adjusted based on the input voltage only. This boost follower implementations increases the efficiency of the downstream DC-DC converter and therefore of the overall power supply. Implementations for both the two-level boost and the linear boost follower (or tracking boost) are described in application note AN-8021.
5. Adjusting the Phase-Management Thresholds
In any power converter, the switching losses become dominant at light load. For an interleaved converter where there are two or more phases, light-load efficiency can be improved by shutting down one of the phases at light load (also known as phase-shedding or phase-dropping operating). The initial phase-management thresholds are fixed at approximately 13% and 18% of the maximum load power level. This means when the output power reaches 13%, the FAN9611/12 automatically goes from a two-phase to a single-phase operation (phase shed or phase drop). When the output power comes back up to 18%, the FAN9611/12 automatically goes from the single-phase to the two-phase operation (phase-add).
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Figure 30. VCOMP vs. tONMAX
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FAN9611 / FAN9612 -- Interleaved Dual BCM PFC Controllers
6. Disabling the FAN9611/12
There are four ways to disable the FAN9611/12. It is important to understand how the part reacts for the various shutdown procedures. a. Pull the SS Pin to GND. This method uses the error amplifier to stop the operation of the power supply. By pulling the SS pin to GND, the error amplifier's non-inverting input is pulled to GND. The amplifier senses that the inverting input (FB pin) is higher than the reference voltage and tries to adjust its output (COMP pin) to make the FB pin equal to the reference at the SS pin. Due to the slow speed of the voltage loop in PFC applications, this might take several line cycles. Thus, it is important to consider that by pulling the SS pin to GND, the power supply is not shut down immediately. Recovery from a shut down follows normal soft-start procedure when the SS pin is released. Pull the FB Pin to GND. By pulling the FB pin below the open feedback protection threshold of approximately 0.5V, the power supply can be shut down immediately. It is imperative that the FB is pulled below the threshold very quickly since the power supply keeps switching until this threshold is crossed. If the feedback is pulled LOW softly and does not cross the threshold, the power supply tries to deliver maximum power because the FB pin is forced below the reference voltage of the error amplifier on the SS pin. Eventually, as FB is pulled to GND, the SS capacitor is pulled LOW by the internal clamp between the FB and SS pins. The SS pin stays approximately 0.5V higher than the FB pin itself. Therefore, recovery from a shut down state follows normal soft-start procedure when the FB pin is released as the voltage across the SS capacitor starts ramping from a low value. Pulling the COMP Pin to GND. When the COMP pin is pulled below the PWM ramp offset, approximately 0.195V, the FAN9611/12 stops sending gate drive pulses to the power MOSFETs. This condition is similar to pulse skipping under noload condition. If any load is still present at the output of the boost PFC stage, the output voltage decreases. Consequently, the FB pin decreases and the SS capacitor voltage is pulled LOW by the internal clamp between the FB and SS pins. At that point, the operation and eventual recovery to normal operation is similar to the mechanism described above. If the COMP pin is held LOW for long enough to pull the SS pin LOW, the recovery follows normal soft-start procedure when the COMP pin is released. If the SS capacitor is not pulled LOW as a result of a momentary pull-down of the COMP pin, the recovery is still soft due to the fact that a limited current source is charging the compensation capacitors at the output of the error amplifier. Nevertheless, in this case, output voltage overshoot can occur before the voltage loop enters closed-loop operation and resumes controlling the output voltage again.
d.
b.
Pull the VIN Pin to GND. Since the VIN sense circuit is configured to ride through a single line cycle dropout test without shutting down the power supply, this method results in a delayed shutdown of the converter. The FAN9611/12 stops operation approximately 20ms to 32ms after the VIN pin is pulled LOW. The delay depends on the phase of the line cycle at which the pull-down occurs. This method triggers the input brownout protection (input under-voltage lockout), which gradually discharges the compensation capacitor. As the output voltage decreases, the FB pin falls, pulling LOW the SS capacitor voltage. Similarly to the shutdown, once the VIN pin is released, operation resumes after several milliseconds of delay needed to determine that the input voltage is above the turn-on threshold. At least one line cycle peak must be detected above the turn-on threshold before operation can resume at the following line voltage zero-crossing. The converter starts following normal soft-start procedure.
7. Layout and Connection Guidelines
For high-power applications, two or more PCB layers are recommended to effectively use the ground pattern to minimize the switching noise interference. The FAN9611/12 incorporates fast-reacting input circuits, short propagation delays, and strong output stages capable of delivering current peaks over 1.5A to facilitate fast voltage transition times. Many high-speed power circuits can be susceptible to noise injected from their own output or external sources, possibly causing output re-triggering. These effects can be especially obvious if the circuit is tested in breadboard or nonoptimal circuit layouts with long input or output leads. The following guidelines are recommended for all layout designs, but especially strongly for the single-layer PCB designs. (For example of a 1-layer PCB design, see the Application Note AN-6086.) General
c.

Keep high-current output and power ground paths separate from analog input signals and signal ground paths.
For best results, make connections to all pins as short and direct as possible. Power Ground and Analog Ground Power ground (PGND) and analog ground (AGND) should meet at one point only. All the control components should be connected to AGND without sharing the trace with PGND. The return path for the gate drive current and VDD capacitor should be connected to the PGND pin. Minimize the ground loops between the driver outputs (DRV1, DRV2), MOSFETs, and PGND. Adding the by-pass capacitor for noise on the VDD pin is recommended. It should be connected as close to the pin as possible.
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FAN9611 / FAN9612 -- Interleaved Dual BCM PFC Controllers
Gate Drive

The gate drive pattern should be wide enough to handle 1A peak current.
To minimize switching noise, current sensing should not make a loop. Input Voltage Sensing (VIN) Since the impedance of voltage divider is large and FAN9611/12 detects the peak of the line voltage, the VIN pin can be sensitive to the switching noise. The trace connected to this pin should not cross traces with high di/dt to minimize the interference. The noise bypass capacitor for VIN should be connected as close to the pin as possible.
Keep the controller as close to the MOSFETs as possible. This minimizes the length and the loop area (series inductance) of the high-current gate drive traces. The gate drive pattern should be as short as possible to minimize interference. Current Sensing
Current sensing should be as short as possible.
(c) 2008 Fairchild Semiconductor Corporation FAN9611 / FAN9612 * Rev. 1.1.3
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FAN9611 / FAN9612 -- Interleaved Dual BCM PFC Controllers
Quick Setup Guide
The FAN9611/12 can be configured following the next steps outlined in this section. This Quick Setup Guide refers to the schematic diagram and component references of Figure 33. It uses the equations derived and explained in Application Note AN-6086. In preparation to calculate the setup component values, the power supply specification must be known. Furthermore, a few power stage components must be pre-calculated before the controller design begins as their values determine the component selections. An Excel design tool is also available to ease calculations.
Input Voltage Sense Divider Brownout Hysteresis Set Gate Drive Resistor Gate Drive Speed-Up Diode Bypass Capacitor for VDD_HF Startup Energy Storage for VDD Current Sense Resistor RIN2 RINHYST RG1, RG2 DG1, DG2 CVDD1 CVDD2 RCS1, RCS2 2.2 47
Step 1: Input Voltage Range
FAN9611/12 utilizes a single pin (VIN) for input voltage sensing. The VIN pin must be above 0.925V (VIN_BO) to enable operation. The converter turns on at a higher VIN voltage (VIN_ON) set independently by the designer. The input voltage information is used for feedforward in the control algorithm as well. The input-voltage feedforward operates over a four-to-one range from 0.925V (VIN_BO) to 3.7V (VFF_UL), as measured at the VIN pin.
Description
From Power Supply Specification: Minimum AC RMS Input (Turn-On) Minimum AC RMS Input (Turn-Off) Minimum Line Frequency Nominal DC Output Output Voltage Ripple (2 * fLINE) Latching Output OVP Nominal Output Power (to Load) Desired Hold-Up Time Minimum DC Output (End of tHOLD) Minimum Switching Frequency Maximum DC Bias (for FAN9611/12)
Name
VLINE.ON VLINE.OFF fLINE,MIN VOUT VOUT,RIPPLE VOUT,LATCH POUT tHOLD VOUT,MIN fSW,MIN VDDMAX PMAX,CH COUT L tON,MAX N IL,PK IO,MAX RZCD1, RZCD2 C5VB RMOT CSS CCOMP,LF RCOMP CCOMP,HF RFB1 RFB2 ROV1 ROV2 RIN1
Value
Pre-Calculated Power Stage Parameters: Estimated Conversion Efficiency Maximum Output Power per Channel Output Capacitance Boost Inductance per Channel Maximum On-Time per Channel Turns Ratio (NBOOST / NAUX) Peak Inductor Current Maximum DC Output Current (to Load) Calculated Component Values: Zero Current Detect Resistor Bypass Capacitor for 5V Bias Maximum On-Time Set Soft-Start Capacitor Compensation Capacitor Compensation Resistor Compensation Capacitor Feedback Divider Feedback Divider Over Voltage Sense Divider Over Voltage Sense Divider Input Voltage Sense Divider 0.95
Figure 31. VIN Turn-on and Turn-off Thresholds At VIN voltages above the 3.7V upper limit (VFF_UL), input voltage feedforward is not possible. The input voltagesense circuitry saturates at this point and the PWM ramp is modulated any longer. Above VFF_UL, the converter's output power becomes a function of the input voltage as shown in Figure 32. It can also be expressed analytically as:
10
Other Variables Used During the Calculations:
VIN POUT_NO_FF PMAX 3.7
2
(5)
0.15
where VIN is the voltage at the VIN pin and PMAX is the desired maximum output power of the converter which will be maintained constant while the input voltage feedforward circuit is operational.
Figure 32. VIN Feedforward Range As can be seen, the converter's output power capability will follow a square function above VFF_UL.
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FAN9611 / FAN9612 -- Interleaved Dual BCM PFC Controllers
Figure 33. Interleaved BCM PFC Schematic Using FAN9611/12
Step 2: Estimated Conversion Efficiency
Use the estimated full-load power conversion efficiency. Typical value for an interleaved BCP PFC converter is in the 0.92 to 0.98 range. The efficiency is in the lower half of the range for low-power applications. Using state-ofthe-art semiconductors, good quality ferrite inductors and selecting lower limit for minimum switching frequency positively impacts the efficiency of the system. In general, the value of 0.95 can be used unless a more accurate power budget is available.
Step 3: Maximum Output Power per Channel
PMAX, CH 1.2 POUT 2
(6)
A margin of 20% has been added to the nominal output power to cover reference inaccuracy, internal component tolerances, inductance mismatch, and current-sense resistor variation to the per-channel power rating.
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FAN9611 / FAN9612 -- Interleaved Dual BCM PFC Controllers
Step 4: Output Capacitance
C OUT(RIPPLE)
C OUT(HOLD)
POUT 4 fLINE,MIN VOUT VOUT,RIPPLE
2 POUT t HOLD 2 VOUT,MIN
2
Step 9: Zero Current Detect Resistors
(7)
R ZCD1 R ZCD2 0.5 VOUT N 0.5mA
(14)
V VOUT OUT,RIPPLE 2
(8)
The output capacitance must be calculated by two different methods. The first equation determines the capacitor value based on the allowable ripple voltage at the minimum line frequency. It is important to remember that the scaled version of this ripple is present at the FB pin. The feedback voltage is continuously monitored by the non-latching over voltage protection circuit. Its threshold is about 8% higher the nominal output voltage. To avoid triggering the OVP protection during normal operation, VOUT,RIPPLE should be limited to less 12% of the nominal output voltage, VOUT. The second expression yields the minimum output capacitance based on the required hold-up time based on the power supply specification. Ultimately, the larger of the two values satisfies both design requirements and has to be selected for COUT.
where 0.5*VOUT is the maximum amplitude of the resonant waveform across the boost inductor during zero current detection; N is the turns ratio of the boost inductor and the auxiliary winding utilized for the zero current detection; and 0.5mA is the maximum current of the ZCD pin during the zero current detection period.
Step 10: Maximum On-Time Setting Resistor
RMOT 4340 10 6 t ON,MAX
where RMOT should be between 40k and 130k. (15)
Step 11: Output Voltage Setting Resistors (Feedback)
RFB2 3V VOUT 3V PFB IFB
(16)
Step 5: Boost Inductance per Channel
L LINE, OFF L LINE,MAX
2 VLINE, OFF VOUT 2 VLINE, OFF
2 fSW, MIN VOUT PMAX, CH
2 VLINE,MAX VOUT 2 VLINE,MAX
(9) (10)
2 fSW,MIN VOUT PMAX,CH
The minimum switching frequency can occur either at the lowest or at the highest input line voltage. Accordingly, two boost inductor values are calculated and the lower of the two inductances must be selected. This L value keeps the minimum operating frequency above fSW,MIN under all operating conditions.
where 3V is the reference voltage of the error amplifier at its non-inverting input and PFB or IFB are selected by the designer. If the power loss associated to the feedback divider is critical to meet stand-by power consumption regulations, it might be beneficial to start the calculation by choosing PFB. Otherwise, the current of feedback divider, IFB should be set to approximately 0.4mA at the desired output voltage set point. This value ensures that parasitic circuit board and pin capacitances do not introduce unwanted filtering effect in the feedback path. If the feedback divider is used to provide startup power for the FAN9611/12 (see AN-6086 for implementation details), the following equation is used to calculate RFB2:
RFB2 3V
Step 6: Maximum On-Time per Channel
t ON,MAX 2 L PMAX, CH
2 VLINE, OFF
2 V
LINE, ON
12.5V 3 0.7V
0.12mA VOUT
(17)
(11)
Step 7: Peak Inductor Current per Channel
IL,PK 2 VLINE,OFF L t ON,MAX
(12)
where 3V is the reference voltage of the error amplifier at its non-inverting input; 12.5V is the controller's UVLO turn-on threshold; 0.12mA is the worst-case startup current required to start operation; and 3*0.7V accounts for the forward voltage drop of three diodes in series of the startup current. Once the value of RFB2 is determined, RFB1 is given by the following formula:
Step 8: Maximum DC Output Current
IOUT,MAX 2 PMAX, CH VOUT
V RFB1 OUT 1 RFB2 3V
(13)
(18)
RFB1 can be implemented as a series combination of two or three resistors; depending on safety regulations, maximum voltage, and or power rating of the selected resistor type.
(c) 2008 Fairchild Semiconductor Corporation FAN9611 / FAN9612 * Rev. 1.1.3
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FAN9611 / FAN9612 -- Interleaved Dual BCM PFC Controllers
Step 12: Soft-Start Capacitor
C SS 5 A C OUT R FB1 R FB2 0.3 IOUT, MAX R FB2
(19)
converter so noise can be effectively attenuated. The recommended fHFP frequency is around 120Hz in PFC applications.
where 5A is the charge current of the soft-start capacitor and 0.3*IOUT,MAX is the maximum output current charging the output capacitor of the converter during the soft-start process. It is imperative to limit the charge current of the output capacitor to be able to maintain closed-loop soft-start of the converter. The 0.3 factor used in the CSS equation can prevent output over voltage at the end of the soft-start period and provides sufficient margin to supply current to the load while the output capacitor is charging.
Step 14: Over-Voltage Protection Setting (OVP)
R OV2 3.5V VOUT, LATCH POVP
(24)
where 3.5V is the threshold voltage of the OVP comparator and POVP is the total dissipation of the resistive divider network. Typical POVP power loss is in the 50mW to 100mW range.
VOUT, LATCH R OV1 1 R OV2 3.5V
Step 13: Compensation Components
CCOMP,LF 4.1V COUT 2 f0 gM IOUT,MAX
2
RFB2 RFB1 RFB2
(25)
(20)
where 4.1V is the control range of the error amplifier and f0 is the desired voltage loop crossover frequency. It is important to consider that the lowest output ripple frequency limits the voltage loop crossover frequency. In PFC applications, that frequency is two times the AC line frequency. Therefore, the voltage loop bandwidth (f0), is typically in the 5Hz to 15Hz range. To guarantee closed-loop soft-start operation under all conditions, it is recommended that:
ROV1 can be implemented as a series combination of two or three resistors; depending on safety regulations, maximum voltage, and or power rating of the selected resistor type.
Step 15: Input Line Voltage Sense Resistors
R IN2 0.925 V V
2
LINE,MAX
2 VLINE,MIN PINSNS
(26)
C COMP,HF 4 C SS
(21)
This relationship is determined by the ratio between the maximum output current of the gM error amplifier to the maximum charge current of the soft-start capacitor. Observing this correlation between the two capacitor values ensures that the compensation capacitor voltage can be adjusted faster than any voltage change taking place across the soft-start capacitor. Therefore, during startup the voltage regulation loop's response to the increasing soft-start voltage is not limited by the finite current capability of the error amplifier.
where 0.925V is the brown-out protection threshold at the VIN pin. VLINE,MIN is the minimum input RMS operating voltage. Its divided down level at the VIN pin corresponds to the 0.925V brown out protection threshold. VLINE,MAX is the maximum input RMS voltage anticipated in the design and PINSNS is the total power dissipation of the RIN1 - RIN2 divider when the input voltage equals VLINE,MAX. Typical PINSNS power loss is in the 50mW to 100mW range.
2 VLINE,MIN 1 RIN2 RIN1 0.925V
(27)
RCOMP
1 2 f0 CCOMP,LF
1 2 fHFP RCOMP
(22)
RIN1 can be implemented as a series combination of two or three resistors; depending on safety regulations, maximum voltage, and or power rating of the selected resistor type.
CCOMP,HF
(23)
where fHFP is the frequency of a pole implemented in the error amplifier compensation network against highfrequency noise in the feedback loop. The pole should be placed at least a decade higher than f0 to ensure that it does not interfere with the phase margin of the voltage regulation loop at its crossover frequency. It should also be sufficiently lower then the switching frequency of the
RINHYST
2 VLINE,ON RIN2 0.925V RIN1 RIN2 2A
(28)
where 0.925V is the threshold voltage of the line undervoltage lockout comparator and 2A is the sink current provided at the VIN pin during line under-voltage (brownout) condition. The sink current, together with the terminating impedance of the VIN pin determines the hysteresis between the turn-on and turn-off thresholds.
(c) 2008 Fairchild Semiconductor Corporation FAN9611 / FAN9612 * Rev. 1.1.3
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FAN9611 / FAN9612 -- Interleaved Dual BCM PFC Controllers
Step 16: Gate Resistors
It is recommended to place at least a 15 resistor between each of the gate drive outputs (DRV1, DRV2) and their corresponding power devices. The gate drive resistors have a beneficial effect to limit the current drawn from the VDD bypass capacitor during the turn-on of the power MOSFETs and to attenuate any potential oscillation in the gate drive circuits.
R G1 R G2 VDDMAX 1.0 A
The FAN9611/12 sources high peak current to the MOSFET gate through RG and DON, where RG is used to control the turn-on transition time. When the MOSFET is commanded to turn off, QOFF conducts, shorting the gate to the source, where the turn-off speed can be controlled by the value of ROFF. Where maximum turnoff time is desired, the value of ROFF can be 0. DON serves the dual purpose of protecting the QOFF baseemitter junction and blocking the MOSFET discharge current from sinking back through the FAN9611/12. In addition to the high-speed turn-off, another advantage of this circuit is that the FAN9611/12 does not have to sink the high peak discharge current from the MOSFET, reducing the internal power dissipation in the gate drive circuitry by a factor of two. Instead, the current is discharged locally in a tighter, more controlled loop, minimizing parasitic trace inductance while protecting the FAN9611/12 from injected disturbances associated with ground bounce and ringing due to high-speed turn-off.
(29)
where 1.0A is the recommended peak value of the gate drive current.
Step 17: Current-Sense Resistors
R CS1 R CS2 0.18V IL,PK
(30)
Figure 34. Recommended Gate Drive Schematic
A speed-up discharge diode that feeds switching current back into the IC is not recommended.
where 0.18V is the worst-case threshold of the current limit comparator. The size and type of current sense resistors depends on their power dissipation and manufacturing considerations.
1 4 2 V LINE,OFF 2 PRCS1 1.5 IL,PK R CS1 6 9 VOUT
(31)
Figure 35. Discharge Diode is Not Recommended
In cases where it is desirable to control the MOSFET turn-on and turn-off transition times independently, the circuit of Figure 36 can be used.
where the 1.5 factor is used for the worst-case effect of the current-limit threshold variation. When the currentsense resistor is determined, the minimum currentsense threshold must be used to avoid activating overcurrent protection too early as the power supply approaches full-load condition. The worst-case power dissipation of the current sense resistor occurs when the current-sense threshold is at its maximum value defined in the datasheet. The ratio between the minimum and maximum thresholds squared (since the square of the current determines power dissipation) yields exactly the 1.5 factor used in the calculation.
Figure 36. Gate Drive Schematic with Independent Turn-On and Turn-Off
(c) 2008 Fairchild Semiconductor Corporation FAN9611 / FAN9612 * Rev. 1.1.3
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FAN9611 / FAN9612 -- Interleaved Dual BCM PFC Controllers
Typical Performance Characteristics -- Supply
Typical characteristics are provided at TA = 25C and VDD = 12V unless otherwise noted.
Figure 37. ISTARTUP vs. Temperature
Figure 38. Operating Current vs. Temperature
Figure 39. UVLO Thresholds vs. Temperature
Figure 40. UVLO Hysteresis vs. Temperature
(c) 2008 Fairchild Semiconductor Corporation FAN9611 / FAN9612 * Rev. 1.1.3
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FAN9611 / FAN9612 -- Interleaved Dual BCM PFC Controllers
Typical Performance Characteristics -- Control
Typical characteristics are provided at TA = 25C and VDD = 12V unless otherwise noted.
Figure 41. Transfer Function (Maximum On Time vs. VIN)
Figure 42. Maximum On Time vs. Temperature
Figure 43. EA Transconductance (gM) vs. Temperature
Figure 44. EA Reference vs. Temperature
Figure 45. 5V Reference vs. Temperature
(c) 2008 Fairchild Semiconductor Corporation FAN9611 / FAN9612 * Rev. 1.1.3
Figure 46. Soft-Start Current vs. Temperature
www.fairchildsemi.com 28
FAN9611 / FAN9612 -- Interleaved Dual BCM PFC Controllers
Typical Performance Characteristics -- Control
Typical characteristics are provided at TA = 25C and VDD = 12V unless otherwise noted.
Figure 47. Phase-Control Thresholds vs. Temperature
Gate Drive 1 Gate Drive 2
Gate Drive 1 Gate Drive 2
Inductor Current 1 Inductor Current 2
Inductor Current 1 Inductor Current 2
Figure 48. Phase-Dropping Operation
Figure 49. Phase-Adding Operation
(c) 2008 Fairchild Semiconductor Corporation FAN9611 / FAN9612 * Rev. 1.1.3
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FAN9611 / FAN9612 -- Interleaved Dual BCM PFC Controllers
Typical Performance Characteristics -- Protection
Typical characteristics are provided at TA = 25C and VDD = 12V unless otherwise noted.
Figure 50. CS Threshold vs. Temperature
Figure 51. CS to OUT Delay vs. Temperature
Figure 52. Restart Timer Frequency vs. Temperature
Figure 53. Maximum Frequency Clamp vs. Temperature
Figure 54. Brownout Threshold vs. Temperature
(c) 2008 Fairchild Semiconductor Corporation FAN9611 / FAN9612 * Rev. 1.1.3 www.fairchildsemi.com 30
FAN9611 / FAN9612 -- Interleaved Dual BCM PFC Controllers
Typical Performance Characteristics -- Protection
Typical characteristics are provided at TA = 25C and VDD = 12V unless otherwise noted.
Figure 55. Non-Latching OVP vs. Temperature
Figure 56. Latching OVP vs. Temperature
Figure 57. OVP Hysteresis vs. Temperature
(c) 2008 Fairchild Semiconductor Corporation FAN9611 / FAN9612 * Rev. 1.1.3
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FAN9611 / FAN9612 -- Interleaved Dual BCM PFC Controllers
Typical Performance Characteristics -- Operation
Typical characteristics are provided at TA = 25C and VDD = 12V unless otherwise noted.
IL1
IL1
IL2
IL2
IL1 + IL2 IL1 + IL2
Figure 58. Ripple-Current Cancellation (110VAC)
Figure 59. Ripple-Current Cancellation (110VAC)
VGATE VOUT
VGATE VOUT
Line Current Line Current
Figure 60. No-Load Startup at 115VAC
Figure 61. Full-Load Startup at 115VAC
Line Vol VOUT COMP Line Current
110VAC
220VAC
Figure 62. Input Voltage Feedforward Note: 6. For full performance operational characteristics at both low line (110VAC) and high line (220VAC), as well as at noload and full-load, refer to FEB279 Evaluation Board User Guide: 400W Evaluation Board using FAN9612.
(c) 2008 Fairchild Semiconductor Corporation FAN9611 / FAN9612 * Rev. 1.1.3
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FAN9611 / FAN9612 -- Interleaved Dual BCM PFC Controllers
Evaluation Board
FEB388: 400W Evaluation Board Using FAN9611/12
FEB388 is an evaluation board for an interleaved dual boundary-conduction-mode PFC converter rated at 400W (400V/1A) power. With phase management, the efficiency is maintained above 96% even down at 10% of the rated output power. The efficiencies for full-load condition exceed 96% as shown below. Figure 63 and Figure 64 show the phase management with the default minimum threshold values of the IC. They can be adjusted upwards to achieve a different efficiency profile (Figure 65 and Figure 66) where phase management thresholds are adjusted to 30% / 44% of the full load. For full specification, design schematic, bill of materials and test results; see FEB388 -- FAN9611/12 400W Evaluation Board User Guide (AN-9717).
Input Voltage
VIN Nominal: 85V~264VAC VDD Supply: 13V~18VDC
Rated Output Power
400W
Output Voltage (Rated Current)
400V (1A)
FIGURE 63.
Measured Efficiency at 115VAC (Default Thresholds)
FIGURE 64.
Measured Efficiency at 230VAC (Default Thresholds)
FAN9612 Efficiency vs. Load
(115 VAC Input, 400 VDC Output, 400W)
100
100
FAN9612 Efficiency vs. Load
(230 VAC Input, 400 VDC Output, 400W)
Efficiency (%)
95
95
Efficiency (%)
With Phase Management
90
With Phase Management
90
Without Phase Management
Without Phase Management
85 0 10 20 30 40 50 60 70 80 90 100
85 0 10 20 30 40 50 60 70 80 90 100
Output Power (%)
Output Power (%)
Figure 65. Measured Efficiency at 115VAC (Adjusted Thresholds)
Figure 66. Measured Efficiency at 230VAC (Adjusted Thresholds)
(c) 2008 Fairchild Semiconductor Corporation FAN9611 / FAN9612 * Rev. 1.1.3
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FAN9611 / FAN9612 -- Interleaved Dual BCM PFC Controllers
Table 1. Part Number
FAN6961
Related Products Description
Green Mode PFC
PFC Control
Single BCM (CRM) Single BCM (CRM) Single BCM (CRM) Single BCM (CRM) Single BCM (CRM)
Number of Pins
8 8 8 8 8
Comments
Industry Standard Pin-Out with Green Mode Functions Industry Standard Pin-Out Low THD for Boost-Follower Implementation Low THD Low THD, Alternate Pin-Out of FAN7529 (Pins 2 and 3 Reversed) PFC Ready pin, Frequency Limit, AC-Line-Absent Detection, SoftStart to Minimize Overshoot, Integrated THD Optimizer, TSD
Dual BCM (CRM), 180 Out-of-Phase, 10.0V UVLO Dual BCM (CRM), 180 Out-of-Phase, 12.5V UVLO
FAN7527B Boundary Mode PFC Control IC FAN7528 FAN7529 FAN7530 Dual Output Critical Conduction Mode PFC Controller Critical Conduction Mode PFC Controller Critical Conduction Mode PFC Controller Critical Conduction Mode PFC Controller
Interleaved Dual BCM PFC Controller Interleaved Dual BCM PFC Controller
FAN7930
Single BCM (CRM)
8
FAN9611 FAN9612
Dual BCM (CRM) Dual BCM (CRM)
16 16
Related Resources
AN-6086: Design Consideration for Interleaved Boundary Conduction Mode (BCM) PFC Using FAN9612 AN-9717: Fairchild Evaluation Board User Guide FEB388: 400W Evaluation Board using FAN9611/12 AN-8021: Building Variable Output Voltage Boost PFC Converters Using FAN9612
References
1. 2. L. Huber, B. Irving, C. Adragna and M. Jovanovich, "Implementation of Open-Loop Control for Interleaved DCM/BCM Boundary Boost PFC Converters", Proceedings of APEC '08, pp. 1010-1016. C. Bridge and L. Balogh, "Understanding Interleaved Boundary Conduction Mode PFC Converters", Fairchild Power Seminars, 2008-2009.
(c) 2008 Fairchild Semiconductor Corporation FAN9611 / FAN9612 * Rev. 1.1.3
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FAN9611 / FAN9612 -- Interleaved Dual BCM PFC Controllers
Physical Dimensions
10.00 9.80 8.89
16 9
A
B
1.75
6.00
4.00 3.80
5.6
PIN ONE INDICATOR
1
8
1.27 (0.30)
0.51 0.35 0.25
M
1.27 CBA
0.65
LAND PATTERN RECOMMENDATION
1.75 MAX 1.50 1.25 0.25 0.10 C 0.10 C
SEE DETAIL A 0.25 0.19
0.50 0.25 X 45 (R0.10) (R0.10) 8 0 0.36 GAGE PLANE
NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AC, ISSUE C. B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH AND TIE BAR PROTRUSIONS D) CONFORMS TO ASME Y14.5M-1994 E) LANDPATTERN STANDARD: SOIC127P600X175-16AM F) DRAWING FILE NAME: M16AREV12.
0.90 0.50 (1.04)
SEATING PLANE
DETAIL A
SCALE: 2:1
Figure 67. 16-Lead SOIC Package
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/.
(c) 2008 Fairchild Semiconductor Corporation FAN9611 / FAN9612 * Rev. 1.1.3
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FAN9611 / FAN9612 -- Interleaved Dual BCM PFC Controllers
(c) 2008 Fairchild Semiconductor Corporation FAN9611 / FAN9612 * Rev. 1.1.3
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FAN9611 / FAN9612 -- Interleaved Dual BCM PFC Controllers
Table 2. Revision
1.0.0 1.0.1 1.1.0 1.1.1
Revision History Date
July 2009 Aug 2009 Apr 2010 May 2010 Initial Release of FAN9612 Preliminary release of FAN9611 product added to the FAN9612 Released datasheet. Updated FB-SS Clamp operation text and input voltage range section. Updated min and max frequency specs. Added note 4 to Max Switching Frequency pg 4. 1. Page 26/ Step 16: Change from "It is recommended to place a low-value resistor..." to "It is recommended to place at least a 15-Ohm resistor between each of the gate drive outputs (DRV1, DRV2) and their corresponding power devices. " 2. Removed ESD data (leaving only the website data, maintained dynamically). 3. Added Figure 35. 4. Modified FEB279 references to FEB388. 5. Added FAN7930 into the Related Products table. Removed the preliminary status of FAN9611 from ordering information
Description
1.1.2
Oct 2010
1.1.3
Mar 2011
(c) 2008 Fairchild Semiconductor Corporation FAN9611 / FAN9612 * Rev. 1.1.3
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